The present invention relates to digital computer systems, and more particularly to a architecture for rapidly accessing data stored in memory.
The evolution of computer system processors has produced a number of refinements which accelerate the rate at which such processors can execute instructions. As a consequence, the delays associated with fetching consecutive instructions from memory have become the primary factor which limit the computer system processing speeds. The delays commonly attributable to fetching instruction data from memory are further exacerbated when multiple processors are configured to access data resident in the same memory. Such problems have become major data processing limitations for contemporary dyadic type processor systems.
Analyses of the memory accessing operations performed by processors have identified that significant segments of the memory accessing operations are used to obtain processor instruction data which follows an ordered address sequence, to the extent that large groups of instructions are commonly resident in memory at sequentially incremented addresses.
In recognition of this ordered arrangement of instruction data addresses, individuals practicing in the technology have developed design refinements which anticipate the existence of sequences and perform anticipatory operations to accelerate memory accessing. An example of such technology appears in U.S. Pat. No. 4,583,162, where a look ahead memory interface is described. The interface according to such patent anticipates the next address to be generated by the processor and then transmits the anticipated address to the memory as soon as access is authorized. The objective is to reduce the memory access time by eliminating memory addressing transients. No data is fetched from the memory based upon the next predicted address. Furthermore, access to the memory by other users, for example, a second processor, is thus foreclosed. Clearly, such interface is likely to result in a net loss of processor capability in any multiple processor computer system.
A somewhat more related arrangement is described in U.S. Pat. No. 4,621,320, where the memory is partitioned and the prefetching is based upon an anticipated address sequence. The prefetched data is stored in a register and conveyed to the processor only after the processor completes a address comparison between the actual succeeding address and the anticipated address represented by the prefetched data. The prefetching, however, in the context of this invention, is only done with reference to one bank of the memory. Consequently, memory access performance gains are minimal. Furthermore, the invention in this patent degrades when used in the context of a multiple processor shared memory computer system because of address translation delays and the need for more bank refresh cycles.
Both the above noted patents compare addresses to determine whether the anticipated next address corresponds to that actually generated by the processor. An inherent deficiency of such arrangements are the time delays associated with the translations of the addresses from their virtual to their real form in the comparison operation.
Accordingly, there exists a need for a memory accessing architecture suitable for operation with multiple processors and virtual addresses characterized by ordered address sequences.